Field
Embodiments of the invention relate to the field of computer-aided design, and more specifically, to design synthesis.
Background
Currently, synthesis tools have problems synthesizing designs larger than a few million gates. In order to synthesize designs larger than a few million gates, users manually partition the design into smaller segments, and then constrain and synthesize each partition separately. All the partitions are linked together to construct the final design. This is commonly referred to as bottom-up synthesis. It is a manual, time-consuming and inefficient process requiring the creation and maintenance of several design projects via scripts. This “traditional” bottom-up flow suffers from the following problems: (1) scripting is complex and error prone, (2) constraints for design partitions must be complete and accurate, (3) boundary optimization is inhibited across partition boundaries, (4) name collisions between shared design partitions cause flow problems, (5) modeling the timing of the design partition for the top-level synthesis is complex, and (6) keeping track of incremental design changes is manual and error prone
Most critical yet error-prone among the various manual tasks is the process of determining constraints for each of the partitions. Incorrect constraint budgeting leads to poor quality of results since synthesis tools do not optimize across the boundary of the partitions and are forced to work with the sub-optimal constraints.
When there is a change in one of these design partitions, using currently available synthesis tools, it is the user's responsibility to keep track of the changes and re-synthesize only the partitions that changed. Alternatively, the synthesis tool will re-synthesize the complete design. Both these solutions are undesirable because of the manual effort involved and the long runtimes incurred by complete, rather than incremental, synthesis.
Therefore, there is a need to have an efficient technique to improve design synthesis of digital circuits.